DRAMs adopting the "folded bit line (two-intersection) construction" generally tend to be highly integrated so as to have their capacity increased and at the same time to be quite fast in operation so as to shorten the time periods for data writing and reading operations. In such a DRAM, the reduction of resistance of the word lines is sometimes an important technical consideration for effecting the high speed. Usually, the word lines are formed at a fabrication step identical to and integrally with the gate electrodes of insulated gate type field effect transistors (which will be abbreviated as "MISFETS") in a fabrication process. Therefore, the word lines are required to endure a variety of subsequent hot heat treatment steps such as a heat treatment step for forming the source and drain regions of the MISFETs or a glass flow step of forming an inter-layer insulating film. Also, such word lines are typically made of a conductive material such as polycrystalline silicon. However, this polycrystalline silicon has a defect in that its sheet resistance is higher than that of aluminum which is generally used to make the wires of a semiconductor integrated circuit. Therefore, the use of polycrystalline silicon for the word lines obstructs acceleration of the operating speed.
In order to reduce the substantial resistance of the word lines to thereby accelerate the operating speed, therefore, a DRAM has previously been proposed which adopts the double-layered aluminum wiring structure (1983, IEEE International Solid-State Circuits Conference Digest of Technical Papers, pages 226 and 227). The DRAM adopting the double-layered aluminum wiring is specifically constructed of: a first polycrystalline silicon layer forming the capacity element of a memory cell; a second polycrystalline silicon layer forming first word lines and the gate electrode of a MISFET; a first aluminum layer forming bit lines; and a second aluminum layer forming second word lines extending in the same direction as the extending direction of the first word lines so as to reduce the resistance of the first word lines. The second word lines are the same in number as the first word lines, and the second word lines and the first word lines are electrically connected through connecting holes, which are formed at a predetermined pitch in their interlayer insulating film, and through an intermediate conductive member which is formed of the first aluminum layer so as to improve coverage of the second aluminum layer.
As a result of the investigation of the technique thus far described, the inventor has found that the DRAM adopting the double-layered aluminum wiring structure has reduced reliability because of difficulties in forming the second aluminum wiring layer in a highly integrated device. In utilizing high integration and the multi-layered wiring, more specifically, a remarkably strict design rule of the second aluminum layer is required for forming the second word lines in accordance with the pitch of the first word lines. In particular, working problems are liable to occur such as, for example, breaking of the second aluminum wires due to growth of undulations in the upper portion of the inter-layer insulating film and failure of masking registration, short-circuiting between the adjoining second aluminum wires due to inferior patterning or inferior connecting between the first and second aluminum wires. Although the above comments are directed to DRAMs, it is to be noted that similar difficulties can be found in other types of semiconductor memories.